The widespread use of object-oriented languages and Internet security concerns are just the beginning. Add embedded systems, multiple memory banks, highly pipelined units operating in parallel, and a host of other advances and it becomes clear that current and future computer architectures pose immense challenges to compiler designers-challenges th
This book constitutes the thoroughly refereed post-conference proceedings of the 34th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2020, held in Delaware, NE, USA, in October 2021. Due to COVID-19 pandemic the conference was held virtually. The 9 revised full papers were carefully reviewed and selected from 11 submissions. The conference covers all aspects of languages, compiler techniques, run-time environments, and compiler-related performance evaluation for parallel and high-performance computing. The scope of the workshop encompasses foundational results, as well as practical experience reports and bold new ideas for future systems.
The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Traditionally, these embedded processors mostly have been pro grammed in assembly languages due to efficiency reasons. This implies time consuming programming, extensive debugging, and low code portability. The requirements of short time-to-market and dependability of embedded systems are obviously much better met by using high-level language (e.g. C) compil ers instead of assembly. However, the use of C compilers frequently incurs a code quality overhead as compared to manually written assembly programs. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice. In turn, this requires new compiler techniques that take the specific constraints in embedded system de sign into account. An example are the specialized architectures of recent DSP and multimedia processors, which are not yet sufficiently exploited by existing compilers.
This book constitutes the refereed proceedings of the 15th International Conference on Compiler Construction, CC 2006, held in March 2006 as part of ETAPS. The 17 revised full papers presented together with three tool demonstration papers and one invited paper were carefully reviewed and selected from 71 submissions. The papers are organized in topical sections.
The purpose of a DIMACS Challenge is to encourage and coordinate research in the experimental analysis of algorithms. The First DIMACS Challenge encouraged experimental work in the area of network flow and matchings. This Second DIMACS Challenge, on which this volume is based, took place in conjunction with the DIMACS Special Year on Combinatorial Optimization. Addressed here are three difficult combinatorial optimization problems: finding cliques in a graph, colouring the vertices of a graph, and solving instances of the satisfiability problem. These problems were chosen both for their practical interest and because of their theoretical intractability.
For real-time systems, the worst-case execution time (WCET) is the key objective to be considered. Traditionally, code for real-time systems is generated without taking this objective into account and the WCET is computed only after code generation. Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided. Among others, the techniques cover source code and assembly level optimizations, exploit machine learning techniques and address the design of modern systems that have to meet multiple objectives. Using these optimizations, the WCET of real-time applications can be reduced by about 30% to 45% on the average. This opens opportunities for decreasing clock speeds, costs and energy consumption of embedded processors. The proposed techniques can be used for all types real-time systems, including automotive and avionics IT systems.
This book constitutes the refereed proceedings of the 4th Mexican International Conference on Artificial Intelligence, MICAI 2005, held in Monterrey, Mexico, in November 2005. The 120 revised full papers presented were carefully reviewed and selected from 423 submissions. The papers are organized in topical sections on knowledge representation and management, logic and constraint programming, uncertainty reasoning, multiagent systems and distributed AI, computer vision and pattern recognition, machine learning and data mining, evolutionary computation and genetic algorithms, neural networks, natural language processing, intelligent interfaces and speech processing, bioinformatics and medical applications, robotics, modeling and intelligent control, and intelligent tutoring systems.
Distributed-memory multiprocessing systems (DMS), such as Intel's hypercubes, the Paragon, Thinking Machine's CM-5, and the Meiko Computing Surface, have rapidly gained user acceptance and promise to deliver the computing power required to solve the grand challenge problems of Science and Engineering. These machines are relatively inexpensive to build, and are potentially scalable to large numbers of processors. However, they are difficult to program: the non-uniformity of the memory which makes local accesses much faster than the transfer of non-local data via message-passing operations implies that the locality of algorithms must be exploited in order to achieve acceptable performance. The management of data, with the twin goals of both spreading the computational workload and minimizing the delays caused when a processor has to wait for non-local data, becomes of paramount importance. When a code is parallelized by hand, the programmer must distribute the program's work and data to the processors which will execute it. One of the common approaches to do so makes use of the regularity of most numerical computations. This is the so-called Single Program Multiple Data (SPMD) or data parallel model of computation. With this method, the data arrays in the original program are each distributed to the processors, establishing an ownership relation, and computations defining a data item are performed by the processors owning the data.